A well known means for synthesizing signals of desired frequencies is the phase-locked loop circuit. Phase-locked loop (PLL) circuits comprise a tunable oscillator and a phase comparator. Typically, a voltage-controlled oscillator (VCO) is used as the tunable oscillator. The output of the VCO is the synthesized signal which is locked to a known reference frequency signal by means of the phase comparator. The phase comparator generates an output signal that is proportional to the phase difference between the synthesized signal and the reference signal. The phase comparator output is fed back to the input of the VCO and used to tune the VCO. The output of the VCO is thereby forced to have exactly the same frequency as the reference signal. Typically, a PLL will also include a loop filter interposed between the phase comparator output and the VCO input through which the phase comparator output signal is fed back to the VCO.
The synthesized signal may also be controlled to have a frequency which is a multiple of the reference signal's frequency by interposing a divide-by-N block between the VCO output and the phase comparator. The output of the VCO will then be locked to a frequency which is N times that of the reference signal. As will be recognized by those skilled in the art of frequency synthesizers, the principles of the present invention apply equally to numerous other PLL circuit topologies that vary from this basic configuration in one or more implementation details.
In many applications, it is desirable to frequency modulate the synthesized signal. However, since the PLL acts to control the frequency of the synthesized signal to maintain a constant phase difference between the synthesized signal and a reference signal, it is difficult to frequency modulate the synthesized signal. Any variation in phase between the synthesized signal and the reference signal, including frequency modulation, tends to be removed by the PLL frequency control.
Several methods of frequency modulating a PLL synthesized signal have been proposed. One such method is disclosed by M. DaSilva, D. Whipple, and R. Temple in U.S. Pat. 4,546,331, issued on Oct. 8, 1985 and entitled "Frequency Modulation in a Phase-Locked Loop." The patent describes a method of accomplishing frequency modulation (FM) of a PLL synthesized signal by splitting the FM signal into two separate signal paths for coupling to the PLL. In the first path, the FM signal is AC coupled to the VCO by interposing a summation node between the phase detector and VCO and connecting the FM signal thereto. This is the primary path for the FM signal for modulation frequencies that are above the bandwidth of the PLL. Frequency modulation of modulation frequencies inside the PLL bandwidth takes the second path.
In the second path, the FM signal is DC coupled to the PLL. The FM signal is integrated and then injected into a summing node at the output of the phase detector. Typically, the integration is accomplished with an analog integrator consisting of an OP-AMP and a capacitor. Since phase is the integral of frequency, frequency modulation within the PLL bandwidth is accomplished by phase modulation. By properly scaling the gain of each signal path, a flat FM response may be provided for modulation frequencies both inside and outside the PLL bandwidth.
Without more, however, this basic circuit would be limited by the phase detector range, integrator range and loop bandwidth which restrict the PLL's modulation index .beta. or amount of phase deviation from the center frequency of the PLL. The modulation index is given by the following equation which relates phase deviation to the amount of frequency deviation. ##EQU1##
U.S. Pat. No. 4,546,331 describes additional circuitry useful for overcoming these limitations to extend the frequency response of the PLL down to zero Hertz. The additional circuitry operates to add or remove one or more cycles of the VCO output from the divide-by-N block input, precisely reset the integrator, and precisely measure the instantaneous phase deviation.
More specifically, whenever the output voltage of the integrator exceeds, positively or negatively, preset threshold voltage levels, a three-modulus prescaler removes or adds one or more cycles at the input to the loop divide-by-N block, effectively removing or adding an integral multiple of two pi radians of phase change to the input of the divide-by-N block. The cycle addition and removal may alternately by implemented by use of separate cycle `swallower` and cycle "burper" circuits interconnected between the VCO output and the divide-by-N block which add or remove a cycle of the VCO output signal before it is applied to the divide-by-N block. A second alternative implementation would be to replace the divide-by-N block with a programmable divider which effects addition of a cycle by momentarily changing the divider's 0 modulus from N to N-1 and removal of a cycle by momentarily changing the modulus from N to N+1.
Concurrently with the cycle addition or removal, the integrator is reset by adding to or removing from the integrator input a precise amount of charge which exactly cancels the amount of phase which has been removed or added at the input to the divide-by-N block. When the integrator is implemented as a combination of an OP-AMP and a capacitor, this is typically accomplished by selectively injecting precise amounts of charge at the input of the OP-AMP.
A remaining limitation to this approach is its frequency accuracy, which is limited by offset voltages and leakage currents in the FM signal path. Any offset at the integrator input translates into a center frequency shift of the output signal of the VCO. To prevent center frequency drift, DC feedback around the integrator is provided through a resistor network. This effectively moves the pole of the frequency response away from zero hertz. Additionally, an up/down counter and digital-to-analog converter (DAC) are utilized to feed back a signal to the integrator input through the resistor network which is proportional to the number of pulses added or removed at the divide-by-N block. The DAC and counter are needed to reconstruct a signal proportional to the phase gained or lost by adding or removing a cycle at the divide-by-N block or in other words, proportional to the exact instantaneous phase deviation of the PLL. This feedback signal is appropriately scaled by the resistor network. The resulting circuit provides AC coupled frequency modulation (ACFM) of the synthesized signal with no center frequency offset.
The foregoing circuitry may also be operated for DC coupled frequency modulation (DCFM) of the PLL synthesized signal by switching off the DC feedback around the integrator and disabling the instantaneous phase deviation feedback signal generated by the DAC and counter. With no feedback, the integrator does not cancel the DC offsets. The loop output frequency will then respond to DC voltages in the FM signal path to provide DCFM of the PLL signal. Unfortunately, with no feedback, any offset in the FM signal path translates into an offset of the center frequency.
One way to correct for offsets in the FM signal path is to add an offset compensation signal to the FM signal path to cancel the offsets present in the path. This method suffers the disadvantage that once the offset compensation signal is set, any changes in the offsets due to temperature drift or other cause will again result in a move of the PLL output frequency away from center.
In accordance with the present invention, a modification to the circuitry in the prior art frequency modulated PLL circuit described above allows the circuit to perform a self-calibration to remove the center frequency offset without manually measuring the frequency or adjusting the offset compensation current. The circuitry of the present invention is thereby capable of DCFM operation without center frequency offset. The circuitry is modified by addition of a feedback register and a memory device. The feedback register is connected between the up/down counter and the DAC. The memory device is connected to the feedback register in order to store a value from the feedback register and to load the feedback register with a stored value. The present invention may be alternately embodied in any configuration of the memory device with the circuit that allows storage of a value from the up/down counter and pre-setting of the DAC feedback signal to a level proportional to the stored value.
The calibration starts by removing any modulation signals present on the FM signal path. Only DC offsets should remain. The counter and DAC are enabled to allow DC feedback around the integrator. With the modulation signals removed, the DAC feedback signal will settle to a level at which a feedback signal equal and opposite to the offsets is generated at the integrator input. After the DAC settles, this feedback signal cancels the offsets and their effect on the PLL output frequency. At this point, the value at the DAC input is held constant so that the DAC feedback signal remains constant. The circuit is then calibrated and ready for DCFM operation. DCFM operation without center frequency drift is possible since the fixed DAC feedback signal remains to cancel the offsets. If the offsets subsequently change, self-calibration should be reinitiated to move the PLL frequency back to center.
The memory device is used to eliminate unnecessary recalibration. Since the AC corner of the integrator is set very low to meet FM requirements, settling time of the DAC feedback signal can be relatively long. It is therefore desirable to avoid unnecessary calibration by performing the calibration process only as a result of a change in the offsets. Accordingly, after a calibration is completed, the value of the fixed DAC input is stored in the memory device. The DAC input can thereafter be preset to the calibrated value at any time. This feature allows DCFM operation to be discontinued and then later resumed without additional repetition of the calibration process and loss of time.
The foregoing and additional features and advantages of the invention will be more readily apparent from the following detailed description, which proceeds with reference to the accompanying drawings.
The foregoing features and advantages of the present invention will be more readily apparent from the following detailed description, which proceeds with reference to the accompanying drawings.